Verilog HDL English A Guide to Digital Design and Synthesis IEEE 1364-2001 Compliant
Palnitkar Samir 2003
Verilog HDL A Guide to Digital Design and Synthesis IEEE 1364-2001 Compliant English - Second - New Delhi, India Pearson Education India January 2003 - 490 p. 20.3 x 25.4 x 4.7 cm Volume
9788177589184
Digital Design with Verilog HDL, Modules and Ports, Gate-Level Modeling, Dataflow modeling, Behavioral Modeling, Tasks and Functions, Useful Modeling Techniques, Timings and Delays, Switch-level Modeling, Defined Primitives, Programming Language Interface, Logic Synthesis with Verilog HDL, Advanced Verification Techniques, Strengths Modeling and Advanced Net Definitions, List of PLI Routines, Formal Definition, Verilog Tidbits--India
621.382 / P11Y
Verilog HDL A Guide to Digital Design and Synthesis IEEE 1364-2001 Compliant English - Second - New Delhi, India Pearson Education India January 2003 - 490 p. 20.3 x 25.4 x 4.7 cm Volume
9788177589184
Digital Design with Verilog HDL, Modules and Ports, Gate-Level Modeling, Dataflow modeling, Behavioral Modeling, Tasks and Functions, Useful Modeling Techniques, Timings and Delays, Switch-level Modeling, Defined Primitives, Programming Language Interface, Logic Synthesis with Verilog HDL, Advanced Verification Techniques, Strengths Modeling and Advanced Net Definitions, List of PLI Routines, Formal Definition, Verilog Tidbits--India
621.382 / P11Y