Verilog HDL A Guide to Digital Design and Synthesis IEEE 1364-2001 Compliant
Material type:
TextPublication details: New Delhi, India Pearson Education India 2003Edition: 2nd EdDescription: 490 pISBN: - 9788177589184
- Advanced Verification Techniques
- Behavioral Modeling
- Dataflow modeling
- Defined Primitives
- Formal Definition
- Gate-Level Modeling
- List of PLI Routines
- Logic Synthesis with Verilog HDL
- Modules and Ports
- Programming Language Interface
- Strengths Modeling and Advanced Net Definitions
- Switch-level Modeling
- Tasks and Functions
- Timings and Delays
- Useful Modeling Techniques
- Verilog Tidbits
- Digital Design with Verilog HDL
- 621.382 P11Y
| Cover image | Item type | Current library | Home library | Collection | Shelving location | Call number | Materials specified | Vol info | URL | Copy number | Status | Notes | Date due | Barcode | Item holds | Item hold queue priority | Course reserves | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Books
|
National Institute of Technical Teachers Training & Research | 621.382 P11Y (Browse shelf(Opens below)) | Available | 50132 |
Browsing National Institute of Technical Teachers Training & Research shelves Close shelf browser (Hides shelf browser)
| 621.382 M616I Introduction to digital and data communications. / | 621.382 M862T Telecommunications survival guide / | 621.382 P117F Fiber-optic transmission networks : efficient design and dynamic operation / | 621.382 P11Y Verilog HDL A Guide to Digital Design and Synthesis IEEE 1364-2001 Compliant | 621.382 P27T Telemetry principles. / | 621.382 P27T Telemetry principles. / | 621.382 P27T Telemetry principles / |
There are no comments on this title.
Log in to your account to post a comment.