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Power efficient design of multiplexer using adiabatic logic / Singh, Richa

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Singh, Richa

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TextLanguage: English DDC classification:

621.38216 S64p

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Cover image	Item type	Current library	Home library	Collection	Shelving location	Call number	Materials specified	Vol info	URL	Copy number	Status	Notes	Date due	Barcode	Item holds	Item hold queue priority	Course reserves
	Books	National Institute of Technical Teachers Training & Research				621.38216 S64p (Browse shelf(Opens below))					Available			047414

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Previous	621.38216 G93B Bit error rate reduction of OFDM system using hybrid approach /	621.38216 G93D Development and analysis of non-linear companding transform for peak to average power ratio reduction /	621.38216 R15P Peak to average power ratio reduction of SCFDMA signal using hybrid technique /	621.38216 S64p Power efficient design of multiplexer using adiabatic logic /	621.3822 A13S Study and implementation of digital signal processing tools. /	621.3822 A58 The application of programmable DSPs in mobile communications /	621.3822 A83 Advanced digital signal processing /	Next

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