TY  - BOOK
AU  - Palnitkar Samir
TI  - Verilog HDL: A Guide to Digital Design and Synthesis IEEE 1364-2001 Compliant
SN  - 9788177589184
U1  - 621.382 second
PY  - 2003///
CY  - New Delhi, India
PB  - Pearson Education India
KW  - Digital Design with Verilog HDL, Modules and Ports, Gate-Level Modeling, Dataflow modeling, Behavioral Modeling, Tasks and Functions, Useful Modeling Techniques, Timings and Delays, Switch-level Modeling, Defined Primitives, Programming Language Interface, Logic Synthesis with Verilog HDL, Advanced Verification Techniques, Strengths Modeling and Advanced Net Definitions, List of PLI Routines, Formal Definition, Verilog Tidbits
KW  - India
ER  -