| 000 | 01044nam a22001937a 4500 | ||
|---|---|---|---|
| 003 | NITTTR | ||
| 005 | 20260220124324.0 | ||
| 008 | 260220b |||||||| |||| 00| 0 eng d | ||
| 020 | _a9788177589184 | ||
| 040 |
_bEnglish _c040 |
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| 082 |
_2second _a621.382 _bP11Y |
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| 100 |
_aPalnitkar Samir _d2003 _qGoel Prabhu |
||
| 245 |
_aVerilog HDL _bA Guide to Digital Design and Synthesis IEEE 1364-2001 Compliant _hEnglish |
||
| 250 | _aSecond | ||
| 260 |
_aNew Delhi, India _bPearson Education India _cJanuary 2003 |
||
| 300 |
_a490 p. _c20.3 x 25.4 x 4.7 cm _fVolume |
||
| 650 |
_aDigital Design with Verilog HDL, Modules and Ports, Gate-Level Modeling, Dataflow modeling, Behavioral Modeling, Tasks and Functions, Useful Modeling Techniques, Timings and Delays, Switch-level Modeling, Defined Primitives, Programming Language Interface, Logic Synthesis with Verilog HDL, Advanced Verification Techniques, Strengths Modeling and Advanced Net Definitions, List of PLI Routines, Formal Definition, Verilog Tidbits _zIndia |
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| 942 |
_2ddc _cBK _esecond _n1 |
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| 999 |
_c35827 _d35827 |
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